Understanding PCIe Link Training

1. Introduction PCIe link training is the process by which a Root Complex (RC) and an Endpoint (EP) autonomously negotiate and establish a reliable high-speed serial link. No software is involved; everything is done by the Physical Layer state machine. The process must solve: Receiver detection: Does anything exist on the other end? Bit lock: Can the receiver lock its clock-data recovery (CDR) circuit to the incoming bit stream? Symbol/block lock: Can the receiver identify symbol or block boundaries? Link configuration: What width and lane ordering to use? Speed negotiation: What is the highest mutually supported data rate? This article focuses on the physical layer (PHY) and explains the LTSSM (Link Training and Status State Machine). 2. System Setup Topology: RC Lane EP Lane Lane0 Lane0 Lane1 Lane1 Lane2 open Lane3 open Expected Outcome: Link width: x2 (limited by the EP) Final speed: Gen3 (8 GT/s) 3. Encoding Fundamentals 3.2 8b/10b Encoding (Gen1 and Gen2) Every 8-bit byte is repla